1. Field of Invention
The invention relates to a buffer controller and management method thereof. More explicitly, the invention provides a buffer controller that utilizes a new linked structure to manage the allocation and release of a buffer memory and the corresponding buffer management method.
2. Related Art
With reference to FIG. 1, normally a buffer memory 30 is installed between a controller and other devices for temporarily storing and managing data. The buffer memory 30 can be an SDRAM (Synchronous Dynamical Random Access Memory), an SRAM (Static Random Access Memory), or a DRAM (Dynamical Random Access Memory). The controller 10 and the buffer memory 30 are further connected with a buffer controller 20 in between. The buffer controller 20 is used to manage data access between the controller 10 and the buffer memory 30 to increase the data processing efficiency.
FIG. 2 is a schematic view of conventional buffer management using the linked list method. When the procedure starts, a pointer 40 points to a first unused buffer register 30.0001 in the buffer memory 30. The unused buffer registers 30.0001 to 30.2048 form a linked structure. That is, the buffer register 30.0001 uses its link node to point to 30.0002, the buffer register 30.0002 in turn uses its link node to point to 30.0003, and so on, until the buffer register 30.2408. The link node of the last buffer 30.2048 points to null, meaning the end of the list. With reference to FIG. 3, the buffer controller 20 has a pointer 40 for recording the address of the first unused buffer register 30.0001. When the procedure starts, the pointer 40 points to the buffer register 30.0001. When the buffers 30.0001 to 30.0003 are continuously stored with data, the pointer 40 has to point to 30.0004 through the link node of the buffer register 30.0003. After the buffer registers 30.0001 to 30.0003 are done in use, the buffer controller 20 releases the link nodes of the buffers 30.0001 to 30.0003 to the beginning of the list, one by one. That is, the link node of the buffer 30.0003 has to be changed from pointing to the unused buffer register 30.0004 to pointing back to the buffer register 30.0003. The buffer registers 30.0002 and 30.0001 are also released in order. From the above description, such a simple releasing process involves complicated hardware operations. The first address, the second address and the segment counter of the released buffer register have to be reported to the buffer controller 20 for the pointer 40 to have correct the pointing control. However, such information occupies some memory space. If a large amount of data is being transmitted, the SRAM load will increase tremendously. Furthermore, the buffer controller 20 is installed with only one pointer 40. Requiring the configuring and freeing actions to always start from the beginning of the list may result in overusing the pointer 40, greatly affecting the management efficiency of the buffer controller 20 over the buffer registers.
For a switch controller as an example, the buffer registers usually allocated as a buffer memory. The sizes of buffer registers can be defined according to different applications. The normal capacity of the buffer register is 128 bytes. For a packet on the Ethernet, the largest length of the packet allowed for transmission is 1522 bytes and the minimal length is 64 bytes. Therefore, one segment may need up to 12 buffer registers for the storage of a packet during transmissions and receptions. It further uses the high-speed transmission property of the SRAM to be the communication bridge between the CPU (Central Processing Unit) and the DRAM for speeding up the transmissions. However, if the switch controller continuously receives largest Ethernet packets, cache memory is needed to effectively ease the load of the linked list. The allowed cache memory is nevertheless limited. Therefore, the load on the linked list in this case is still too much and the buffer releasing process is still very slow in speed. It is thus necessary to find another more efficient management method that satisfies the growing demand for a fast network.